In a typical TDMOS device with a trench gate structure, a gate oxide layer is formed on the bottom and sidewalls of the trench, and a channel region between source and drain is formed on the sidewalls of the trench. A current flowing between the source and drain flows vertically along the sidewalls of the trench.
In this TDMOS device, if the trench is not formed with a smoothed shape at the bottom edges, or if the trench is formed having a vertical shape thereat, electric field can be concentrated there, and thereby a leakage current of the gate oxide layer is increased. As a result, the insulation characteristic of the gate oxide layer is deteriorated disproportionately.
It is difficult to fabricate a trench having a smoothed shape at an edge of bottom. A technique for addressing this problem has been disclosed in the invention entitled "TRENCH GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR" in U.S. Pat. No. 5,142,640.
Also, since the trench has a vertical shape even at the top edges thereof, the above-mentioned problem is caused. A technique for addressing this problem has been disclosed in the invention entitled "METHOD FOR FORMING CAPACITOR IN TRENCH OF SEMICONDUCTOR WAFER BY IMPLANTATION OF TRENCH SURFACE WITH OXYGEN" to Levy in U.S. Pat. No. 5,183,775 published in Feb. 2, 1993.